PCIe bus master random access to all host memory

I'm now trying to get this to work, and of course it doesn't.

I don't need high throughput but do need long TLPs (read and write) and asynchronous operation (controlled by a nios cpu).

The 'simple' DMA controller ought to work, but when I request a transfer all that happens is the 'BUSY' bit in the status register is set.

Unfortunately it is a bit difficult to connect the JTAG port to the board I'm using, making signaltap unusable.

It might just be that I've configured the DMA controller incorrectly (in sopc).

I haven't found any info into the required parameters for PCIe DMA.

I decided that the 'best bet' was to 'enable burst transfers' and I set the 'maximum burst size' to 128.

There is some strange comment in the documentation that the maximum transfers length

must be less than the maximum burst length - is this really true?

The longest transfer I need to do is 0x120 bytes, most will be shorter.

Possibly I should be enabling (and using) 64bit transfers?

Any ideas what I've done wrong?

The SGDMA is overcomplex for what I need.