PCIe bus master random access to all host memory

You need to use one of the dma controllers to do the burst writes into the Avalon slave interface of the PCIe block.

Before requesting the transfer you'll need to set the address translation tables so that the correct physical address bits are used.

Last time I looked none of the DMA controllers supported 64bit addressing on one port, so it isn't possible to avoid the address translation tables in the PCIe block.

I also remember having difficulty configuring 32bit address transparancy.

I can't imagine that you'd want to link the PCIe Avalon slave to a normal master (like a nios cpu) - since you really don't want to stall while the transfer tales place. Better would be a 'single transfer (degenerate) DMA controller' to which you write the physical address and data and then poll for completion.

Another useful item would be a memory block that is dual ported as an Avalon slave and to 'PCIe dma logic'. You could then arrange for the data to be in this special memory block and directly request a PCIe transfer to/from it. This would save resources and reduce latency.

Unfortunately Altera don't seem to be making this easy to use.