PCIe bus master random access to all host memory

We have started a new design using Qsys targeting a Stratix V and have arrived at the same dilemma. In fact, I had come up with almost the same possibilities you listed to work with the Avalon-MM Stratix V Hard IP for PCI Express. I’ve begun considering the unpleasant option of trying to use the Avalon-ST version of the PCIe Hard IP and developing our own TLP encoders and decoders, DMA controllers, etc. I’m very curious which solution you ended up using, ijabbott. Cheers!