PCIe bus master random access to all host memory

Quoting last two posts (different authors):

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The above is just my understanding and may be partly or completely wrong.

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I think you are quite right there.

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This can only really be done if the DMA controller in integrated into the PCIe master logic.

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There are a lot of optimizations and removal of limitations if the SGDMA controller is integrated in the PCIe master logic. Arbitrary access to 64-bit host memory is just one thing.

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... I'm interested in how the Lancero solution compares to the Altera offerings.

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I don't think this forum is meant to discuss Altera Partner IP, so I consider to look at its web page and ask.