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Altera_Forum
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14 years ago

PCIe - refclk connection

When implementing PCIe using Qsys on a Cyclone IV GX, should there be a PLL between the refclk pin (100 MHz from connector) and the PCIe IP block? Reference designs do not seem to have one. When I ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I'm targeting a Stratix IV but it's probably the same. The IP instantiates it's own plls so I run the clock input from the pins to the Ip block without a pll. Make sure your clock input in on a clock pin.