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Altera_Forum
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16 years ago

PCI Express Tx interface gets stalled

Hi, I'm still trying to send data (A/D samples) from my PCI Express endpoint (S4 GX Dev. Kit. -> Hard IP) to the root port memory (RAM). I'm able to receive data from the root port, and also...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I think so.

I assumed the byte enable bits are used to mark data as "garbage".

But from your explanation I understand that when using the 3DW header together with the QWORD aligned address (like 1000h) I have to insert a "garbage" DWORD (DW3), and set the 1st DW enable to all ones (since all my real data is valid)?

This "garbage" DWORD doesn't count to the payload length since it won't be send over the link, right?