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Altera_Forum's avatar
Altera_Forum
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16 years ago

PCI Express Tx interface gets stalled

Hi, I'm still trying to send data (A/D samples) from my PCI Express endpoint (S4 GX Dev. Kit. -> Hard IP) to the root port memory (RAM). I'm able to receive data from the root port, and also...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks for your patience, but I'm affraid I still haven't fully understood it :rolleyes:

What I wanna do is to fill a buffer that is page aligned (starts at a memory page border for example 1000h) continuously with data.

Since my memory address is 32 bits I have to use a 3DW header (using 4 DW header with the 32 MSBs set to zero would be treatet as a malformed TLP by the receiver). According to your explanation the addr. 1000h is QWORD aligned, and thus I would have to insert an invalid (byte enable set to zero) DW3? But when I do so the address where the first valid DWORD will be put is (according to the attached image from the PCIe system arch. book) not 1000h, but 1004h?

Maybe this doesn't have anything to do with the original problem of the Tx interface to get stalled, but I just wanna make sure...