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Altera_Forum's avatar
Altera_Forum
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16 years ago

PCI Express Tx interface gets stalled

Hi, I'm still trying to send data (A/D samples) from my PCI Express endpoint (S4 GX Dev. Kit. -> Hard IP) to the root port memory (RAM). I'm able to receive data from the root port, and also...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

But you said that when I use a 3 DW header the addr. is/has to be NON QWORD aligned (the 3 LSBs are 100b) which means I'm starting at the second DWORD?

Maybe there is something wrong with my entire concept?

I don't use a DMA core like in the reference design... I'm using WinDriver to create a continuous buffer in memory, and send the physical address of the buffer to endpoint. Then I set a enable flag in my endpoint from within the driver, and from that point the endpoint keeps sending the sampled data to the root port memory (the mentioned buffer) until it is disabled. From my understanding of PCI Express this should work, but maybe I'm wrong?

I've also been digging for some software that can be used to debug the PCI Express bus, and found this utility that can be used to analyze the PCI Express configuration space (btw. its for free)

http://www.lecroy.com/protocolanalyzer/protocoloverview.aspx?seriesid=193&capid=103&mid=511

Maybe this will help me figuring out what is going wrong.