Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

PCI Express Tx interface gets stalled

Hi, I'm still trying to send data (A/D samples) from my PCI Express endpoint (S4 GX Dev. Kit. -> Hard IP) to the root port memory (RAM). I'm able to receive data from the root port, and also...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I see, but wouldn't this mean that I can't write to the first DWORD of a memory page for example?

Since memory write requests are not allowed to cross a page boundary I can't just set the address to the last DWORD of the page before, and insert an invalid DWORD (by setting the byte enables for the first DW to zero).

Have you/Has someone done something similar (writing from the endpoint to the root port memory) using the hard IP in the StratixIV GX Dev. Kit?