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Altera_Forum's avatar
Altera_Forum
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16 years ago

PCI Express Tx interface gets stalled

Hi, I'm still trying to send data (A/D samples) from my PCI Express endpoint (S4 GX Dev. Kit. -> Hard IP) to the root port memory (RAM). I'm able to receive data from the root port, and also...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The key is that the waveform in figure 5-14 applies to 3 Dword header TLPs with NON-Qword aligned addresses. There is a comment about this in the text immediately above the waveform. This comment implies the address restriction I mentioned in the previous post. I hope this helps.