Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

PCI Express Tx interface gets stalled

Hi, I'm still trying to send data (A/D samples) from my PCI Express endpoint (S4 GX Dev. Kit. -> Hard IP) to the root port memory (RAM). I'm able to receive data from the root port, and also...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I'm sorry, but I don't get it. Why do my 3 addr. LSBs need to be 100b for the waveform in figure 5-14? I couldn"t find any note regarding this in the user guide right now. The two LSBs have to be zero for sure since the address is a byte address, and we're talking about DWORDs...