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Altera_Forum's avatar
Altera_Forum
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16 years ago

PCI Express Tx interface gets stalled

Hi, I'm still trying to send data (A/D samples) from my PCI Express endpoint (S4 GX Dev. Kit. -> Hard IP) to the root port memory (RAM). I'm able to receive data from the root port, and also...
Altera_Forum's avatar
Altera_Forum
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16 years ago

One quick follow up to the question about data alignment. Since Data0 is in DW3 (and header is in DW0-2), then the 3 lsbs of your address (including the two reserved bits must be: 2b'100. If the 3 lsbs of your address was 2b'000, then your data alignment would look like Figure 5-6 on page 5-9.

You should be able to use lspci on linux to read the PCIe capability registers. If you are using windows, there must be some utility analogous to lspci that you can use. I don't know how it would be possible to query the root port status the way you propose (I am not saying it isn't possible...this is just outside the bounds of my knowledge)