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Altera_Forum
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16 years ago

PCI Express Tx interface gets stalled

Hi, I'm still trying to send data (A/D samples) from my PCI Express endpoint (S4 GX Dev. Kit. -> Hard IP) to the root port memory (RAM). I'm able to receive data from the root port, and also...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I'm aware that the payload length field in the header contains just the amount of payload DWORDs, and not also the header.

I Just wanted to point out that I'm using a 3 DW header (because my destination memory addr. is 32 bits), and this results in an odd number of payload DWORDs (since the 2nd QWORD [I'm using Avalon-St interface with 64 bits] contains the 3rd DWORD of the header and also the 1st DWORD of the payload).

@ (1): the alignment of my payload data looks exactly like in figure 5-14 on page 5-15 of the user guide

@ (2): I'm using 64 bit Avalon-St interface

Is it possible to determine the root ports status from the endpoing e.g. by reading the "PCI Express Advanced Error Reporting Capability Structure"?

edit: uploaded the waveforms captured with signaltap to

http://rapidshare.com/files/376204701/datagrabber.vwf