PCI Express Tx interface gets stalled

Maybe this isn't what you meant, but your post seemed to indicate that you were accounting for the header in your payload length. The header should not be included in the payload length field. Sorry if this isn't what you meant...I just wanted to be sure.

Here are a few other things that could potentially affect core behavior (and them impact system behavior as a result)l:

(1) Are you properly aligning the payload data on your tx_st_data bus as described in the "Mapping of Avalon-ST Packets to PCI Express" section starting on page 5-15 of the v9.1 SP PCIe Compiler User Guide? If the payload alignment doesn't line up with the address you send in the packet header, I don't know what the core will do.

(2) If you are using a 128-bit core, are you setting the tx_st_empty signal if the upper 64-bits of your last AV-ST word do not contain valid data?