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Altera_Forum's avatar
Altera_Forum
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16 years ago

PCI Express Tx interface gets stalled

Hi, I'm still trying to send data (A/D samples) from my PCI Express endpoint (S4 GX Dev. Kit. -> Hard IP) to the root port memory (RAM). I'm able to receive data from the root port, and also...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

OK. Keep me posted.

I think the malformed TLP text you were reading is referring to requests from the system to the PCIe core, not the other way around. What this text (on 4-57) is saying is that your application h/w will never see any packet which the PCIe core has received and determined to be malformed.