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Altera_Forum's avatar
Altera_Forum
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16 years ago

PCI Express Tx interface gets stalled

Hi, I'm still trying to send data (A/D samples) from my PCI Express endpoint (S4 GX Dev. Kit. -> Hard IP) to the root port memory (RAM). I'm able to receive data from the root port, and also...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I don't know that I can tell you what is going on, but it might be a good idea to observe the tx_cred vector given to you from the core. This will let you know if you have run out of posted header or posted data credits. If you are out of credits, this would cause the fifo to backup and assert the fifo full signal.

tx_cred is documented in Table 5-4 on page 5-13 of the PCI Express Compiler User Guide (v9.1). The fields of the vector are shown in Table 5-5.