Altera_Forum
Honored Contributor
18 years agoPCI Express translation
Hello,
I have a problem to understand how you calculate the DLLPs CRC in the Altera PCI Express Megacore function. I ran the testbench generated and I took the first 4 bytes of some DLLPs and I applied the 16bits CRC algorithm based on 0x100B polynom with an initial value of 0xFFFF. And I didn't generate the proper result with any DLLPs. Need I to descramble them to do it properly or not? It's with the XIO1100 PHY. Could you help me with that? Secondly, why do I receive, with this PHY, the logical idle scrambled ? Normally it should be unscrambled by the PHY before provided to my Cyclone II FPGA ? Thank you very much for your support.