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Altera_Forum
Honored Contributor
15 years agoHi,
Can any one suggest how we can simulate PCIE SOPC design example using SystemVerilog/VMM based environemt under Synopsys VCS compiler? I assume the follwoing: 1) Endpoint as RTL (DUT) 2) Root Port (RP and VC) as BFM 3) How can driver be used thru an interfcae to the BFM. Thanks. Regards, Muhammad