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Altera_Forum
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15 years ago

PCI Express root port and Avalon MM

Hi everyone! We have a system with multiple boards connected together on a backplane. We currently use a proprietary parallel bus interface between the boards, and I am trying to evaluate the i...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Altera's PCIe Core always functions on 64-bit address alignment, and if you access something that isn't 64-bit aligned (say, byte address 0x04), it will add padding to make it 64-bit aligned.

What comes out of the ST-fifos isn't the "real" TLP, it's padded version. See the section "Mapping of Avalon-ST Packets to PCI Express" in the PCI Express Compiler User's Guide.