PCI Express root port and Avalon MM

Hi everyone!

We have a system with multiple boards connected together on a backplane. We currently use a proprietary parallel bus interface between the boards, and I am trying to evaluate the impact of changing it to PCI Express.

In our most basic setup, we would have one of the boards with a Nios CPU, and the other boards with simpler designs, written entirely in HDL. From what I understand, the board with the Nios would need to be configured as a root port on the PCI express bus, and the other boards as endpoints. I like the way the PCI Express IP from Altera is using the Avalon MM interfaces to have an almost transparent link from the CPU to the peripherals, being able to map the components directly in the CPU's address space. But if I read correctly table 1-2 in the PCI Express compiler datasheet, I can't have the root port with the MM interfaces, I need to use the Megawizard flow instead, and the Avalon streaming interfaces.

Does it mean that if I want to use the Nios as root, I need to make myself a translator between the MM requests and the stream interface on the PCI express IP? This looks quite complicated. I wonder if I shouldn't choose a hard core CPU for my main board instead, such as a Freescale processor. Or am I missing something?

Thanks!