Honored Contributor
Honored ContributorNot entirely related but ...
We seem to be hitting a problem with the PCIe 'slave' side and bus widths. A 32bit write cycle coming into the board ends up as two write cycles (for adjacent addresses, but with the same data) by the time it hits our custom Avalon MM slave. It seems to me that the SOPC builder has dropped in a bus width adapter somewhere that is converting from 64bit to 32bit - although why there is anything 64bit in there seems rather unexpected to me. This particular peripheral ignores the byte-enable lines, but the hw guy here says he saw all the byte enable lines asserted for another peripheral. In any case the bus width adapter will seriously slow down the cycles (the two write cycles are 8 clocks apart (100MHz) so the 400MHz ppc that is mastering the cycle will be spinning for a long time).
