PCI Express IP Hard core reference clk

I wouldn't expect to see anything further from L0 until the operating system on the Keystone probes the PCIe bus to enumerate devices. Do you have e.g. a Linux install and access to /sbin/lspci or similar? The device should show up as enumerated with the device/vendor codes you specified in the core. Actually generating read/write transactions from the host requires you either write a device driver or use Dave's excellent PCI pci_debug tool to access the bar memory space via. /sys/ filesystem.