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Altera_Forum's avatar
Altera_Forum
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12 years ago

PCI Express IP Hard core reference clk

Hi, I'm implementing PCI Express in Cyclone 5 GX and I have a question - I'm using lane 0 therefore TX and RX are connected to GXB_RX_L0 and GXB_TX_L0, but due to the pcb routing I can't connec...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Are you using the QSYS generated Core, and which varient if you are (streaming, or MM)? I've only worked with the QSYS-MM PCIe core.

Is your root port a computer or another FPGA?