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Altera_Forum
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12 years ago

PCI Express IP Hard core reference clk

Hi, I'm implementing PCI Express in Cyclone 5 GX and I have a question - I'm using lane 0 therefore TX and RX are connected to GXB_RX_L0 and GXB_TX_L0, but due to the pcb routing I can't connec...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi shuckc,

Thanks, the link is up now (ltssmstate = L0) but still don't see any data going out from hard IP core. How can I debug and see whether anything is coming to Hard IP and/or get discarded?

Best regards,

Dominik