PCI Express IP Hard core reference clk

REFCLK has to be exactly 100Mhz, or exactly 125Mhz, with fairly tight jitter margins. You select which when you parametrise the core, which selects the fixed ratio between REFCLK and the data clock. You should be using the same clock source (crystal, whatever) for both the to the root port and slave - the phase relationship needs to be constant over time. You normally carry the refclock alongside the data lanes, not generate it locally (otherwise your frequency/phase is not going to match the other source).

For using REFCLKL1, I would just assign that pin to be your refclk, set the part correctly and see if the fitter gives you an error. It will know if the HSSI clock mux settings cover this arrangement better than we do.