PCI Express compiler losing lock on FPGA + simulation

Hi,

After running a few tests on our design that used the pci express compiler, it looks like the pci express interface is losing sync or something (sorry, I'm not familiar with pci express, so that could be entirely wrong). After we see the RECOVERY.RCVRLOCK notice below, DETECT.QUIET, DETECT.ACTIVE and POLLING.ACTIVE repeat indefinitely, and we can no longer transfer to/from the design over the pci express bus.

We're seeing a similar stall on the FPGA at rougly the same point in time. We think it's related to this.

Does anyone know what's happing in the pci express compiler when this occurs, and what could be causing it? TxInterface is not connected to anything, nor is the control register access (but read/write signals are deasserted as well as any chipselects).

# INFO: 280551 ns EP LTSSM State: RECOVERY.RCVRLOCK # INFO: 293399 ns EP LTSSM State: DETECT.QUIET # INFO: 296615 ns EP LTSSM State: DETECT.ACTIVE # INFO: 296679 ns EP LTSSM State: POLLING.ACTIVE # INFO: 309543 ns EP LTSSM State: DETECT.QUIET

Thanks,

baver