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Honored Contributor
Honored ContributorPCI express - Clk Ref, application clk and recailbration clk
Hi all, I'm doing a new board in which we have chosen to use Qsys and in particular a PCIe Requester/Completer. I'm at preliminary phase and reading the user guide it is state a lot of time th...
Altera_ForumHonored Contributor
Honored ContributorOk, it was only some nomenclature.
I think of about Clock Ref as the specific pin of the FPGA that can feed the transceiver block. That's clock will be always present and it is from it (routed also to another global pin of the FPGA) that I enter in a PLL that derive 125MHz and 50Mhz. All shall work. Thx for suggestions
