PCI express - Clk Ref, application clk and recailbration clk

The PLD_CLK is derived from the Link, i.e. this passes through Lock to Reference to Lock to Data, Hence during link training and transceiver calibration the PLD_CLK may not be stable yet. Hence the reconfig_clk, required for transceiver offset calibration, and the fixedclk required for speed negotiation, must be supplied by a seperate clock that is stable at device power-up.

# Note that in "Figure 7-1. Internal Reset Modules in the Hard IP Implementation"of the PCIe User Guide (page 178), the shown "free_running_clock 100MHz" doesn't actually need to be 100MHz, as it is being used as the source for the PLL, any free running clock frequency can be used. Simple modify the PLL settings to match your alternative free running clock frequency.

User Guide Link given below:

http://www.altera.com/literature/ug/ug_pci_express.pdf