Forum Discussion
Altera_Forum
Honored Contributor
17 years agoNot sure what is wrong. PCIE_example_chaining_top.vhd should be the top level file for the design. I have never tried making and using a .bdf file before.
What happens if you open and compile the PCIE_example_chaining_top.qpf project file? That should give you the complete design. You should be able to just make the pin assignments for your board in this project.