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Altera_Forum
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8 years ago

Parallel Flash Loader (PFL) IP Core Timing Constrains

Hallo Everyone I am making a Parallel Flash Loader (PFL) IP core for MAX V device. I have some problems in constraining the design with the timing. In the following link it is mentioned that ...
Altera_Forum's avatar
Altera_Forum
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8 years ago

thanks a lot for your reply. This solves the problem. So if i understood you correctly

output false paths should be set with the command set_false_path -to

input false paths should be set with the command set_false_path -from

I tried this two command on my input and output ports false paths and it works.