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Altera_Forum
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8 years ago

Parallel Flash Loader (PFL) IP Core Timing Constrains

Hallo Everyone I am making a Parallel Flash Loader (PFL) IP core for MAX V device. I have some problems in constraining the design with the timing. In the following link it is mentioned that ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I don't understand why you're doing this:

set_false_path -from [get_clocks *] -to [get_ports {flash_nce}]

It should be simply:

set_false_path -to [get_ports {flash_nce}]

Same with all your output false paths.