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Altera_Forum
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8 years ago

Parallel Flash Loader (PFL) IP Core Signals

Hallo I am making a PFL IP core for a MAX V CPLD. When i look at the user guide on the following link https://www.altera.com/documentation/sss1411439280066.html#sss1458191622012 there...
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Altera_Forum
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8 years ago

Did you enable the parameter for it in the parameter editor? Page 40 of the PDF says the parameter is named "Include input to force reconfiguration".