Parallel Flash Loader function

Thank you FvM for your answer.

We made some measurements with an oscilloscope. Putting the probes on MAX II pins we observed the following things:

1) at power up it continue to try to configure the FPGA. It fails and this is due to the incorrect page 0 configuration (it fails the verify after loading into flash via pfl). Owing to this, conf_done is never released

2) with reference to figure 11-6 on page 11-4 of stratix III handbook, all measured signals (nConfig, nStatus, DCLK) are inside tolerance range for timing; voltage and overshoot seem ok too

We've then kept focus on the bus between the flash and max II and, using again the probes, we found that:

1) on the rise of nconfig the PFL inside MAX II reads at base_address_option_bits+0x80 which contains ff03 (did not found any reference on AN386 but I must re-read)

2) read locations base_address_option_bits and base_address_option_bits+2 and reads expected values (start address and end address of page 0)

Basing on experience with CFI flash decives, we suspected a timing violation on programming cycles particularly thinking about the lot of ones and the fewer zeros seen with u-boot.

We made quartus programmer to configure the flash via PFL on max II and we seen:

1) during erase cycles before programming, the pfl (or quartus II via Jtag) a polling of reads is done probably to verify the erase of the single position has been done successefuly

2) during programming, only write cycles are done (no polling) and write cycles are done with short time intervals measured (with oscilloscope) between 10 us and 57 us; those values seem shorter than the conventional word programming times (200 us reported on Intel/Numonyx P30 data sheet)

thanks,

gabrigob