Parallel Flash Loader function

Hello,

I have a couple of problem with the Parallel Flash Loader on a custom board. First, I describe my conditions:

1) Stratix III FPGA (ep3se110f1115i3) to be configured via Fast Passive Parallel

2) MAX II ( EPM570F100) to configure the FPGA and the flash; due to space saving needs I use the access mode in normal mode (no bursts)

3) Quartus II 9.0 (no sp, no patches)

4) usb blaster (both rev b and rev c)

5) Intel P30 flash

Then I try so summarize my observations:

1) via JTAG I can access the fpga and correctly configure it so I think it is in a good health state

2) via JTAG I can access the MAX II and configure it

3) once configured the MAX II with a PFL I can examine the flash chip and I see it is correctly identified

4) with Quartus programmer I try to write the Option Bits via MAXII and it is done

5) as above with page 0 but the verify fails (fpga not programmed). I observed that the writing phase is very quick... I suspect this is too quick: watching the flash content with u-boot from the FPGA after a failed writing I find quite all bits still set to 1 and some bits (the position seems random) to 0.

6) tried to instantiate a PFL in an FPGA project... same results. (MAX II erased to prevent concurrent writings)

7) tried to write the Option Bits with PFL and page 0 via u-boot on fpga. The flash content has been updated and checking manually some parts of the .rbf file with the bits in memory has given positive results. Anyway after reprogramming MAX II and a power down cycle the FPGA is not programmed.

Anyone has suggestions?

Thanks for attention,

gabrigob