Output Latency for Integer Arithmetic Megacore at Cyclon Family

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I do not know what Output Latencies are valid for a Cyclon V Device for the Interger Arithmetic Megacore Functions, so I used the worst case values I found in the User Guide for pipelining the functions.

Has anybody some hints, how I can find out the correct / optimized values for the Cyclon Family?

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pipelining the core is not matter specific to a device. You have options of pipeline from 0 to whatever and you choose whatever helps your design achieve speed. If you start with a pipeline of 1 and it failed timing at the core then go up to 2 and so on.