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Altera_Forum
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14 years ago

on-chip memory timing diagram

Hi I need have to continuosly update sections of an onchip memory on a regular basis as quickly as possible. I'm using a 125MHz clock. My problem is the datasheet of the onchip MF is quite vague on t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

hi Kaz, thanks for the tips but even if i've got registers at the i/p ,o/p and address how lond do i need to wait to update them with the next data? i've got tons of inputs all trying to access the RAM via one address port. Is there some form of acknowledge that can tell me if one gets written so i can send the next one? if not how long shd i pulse it to be sure the data is written before writing the next one?