Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

On Board RAM and Native PHY Transceiver Core

Hello Everyone! I am trying to implement a transmitter by using Stratix V GT Evaluation Board. I am using 4 channel and 1 Native PHY IPCORE. The data which will be transmitted comes from an ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

--- Quote Start ---

I believe you mean onchip ram (rather than onboard ram).

It could be timing problem on mux or memory editor bug or your testing.

Try mif in each of four rams to bypass editor prblems

--- Quote End ---

Hello Kaz,

I actually use MIF to upload to ram. What I do not understand is that how can 1 RAM work while 4 RAM does not?

Kind Regards