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Have you tried memory testing the SRAM using Nios by itself? It almost sounds like the off-chip timings are incorrect and you are reading data too late.
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Talking about timings made me check my timequest settings, they were wrong. After fixing them, I'm now failing timing with a Recovery path between read_from_addr on the clk domain and the output of the VGA pixel fifo (from the verilog in the first post)
slack: -2.156 ns
from_node: nios2:u0|VGA_Controller:vga_controller|fbAddr[7]
to_node: nios2:u0|VGA_Controller:vga_controller|VGA_driver:VGA0|vga_dram_master:DM0|vga_pixel:F1|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_c1l1:auto_generated|altsyncram_mv61:fifo_ram|q_b[0]
launch clock: P0|altpll_component|auto_generated|pll1|clk[0] (my 90 MHz system clock)
latch clock: P0|altpll_component|auto_generated|pll1|clk[2] (the VGA pixel clock - 40 MHz)
I don't really understand what is happening here - I have the register 'currAddress' in between the input 'read_from_addr' (which is driven by fbAddr). So why is timing failing on this path, when it shouldn't even exist? Shouldn't there be a node 'currAddress' in the middle of that path?
The SRAM issue is probably a symptom of this problem - when I was running the FPGA again today, the offset was different.
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