Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

No output data of CVI IP core.

Hi guys,

First off, I just started using FPGAs about a month ago, and am only just beginning to use Nios II and IP Cores, so suffice to say I am very new to this.

I'm working with CVI IP core to convert the input video from PAL Camera to Avalon-ST video stream,followed by a Deinterlacing IPcore.However,though CVI successfully detected the input clocked video,there is no output.

but when I replace the CVI with Test Pattern Generator IP Core,the datapath works successfully,which has confused me for a long time.

If you've successfully used this in the past, please have a quick read and see if you can help me out.

Thanks a lot!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Anyone? I have problems with clocked video input IP as well...

    Thanks in advance.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi Richeal,

    I has been a while since you posted your issue, but I was wondering whether you fixed it or not? I have clocked video input working now so I might be able give you some pointers by now.

    Grtz, Richard.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hey Guys,

    I am also seeing the similar issue. I do not see any output on the CVI block. I have signal tapped and verified the input to the CVI block and input seems to be fine. Any inputs?

    Regards,

    Hanumanth