no free buffers for rx

If your bursts of packets are well spaced out (in time), then some sort of DMA engine to copy them from the RX FIFO into external memory (from where the IP stack would process them) might help for 100M ethernet, for Ge you don't stand a chance (external memory isn't fast enough).

I don't know if there is one available (I've not looked at the TSE MAC). But, if you aren't that tight for fpga resources, you could use a nios cpu as a custom dma controller. A single M9K block dual ported to tightly coupled I & D ports should be enough code/data. You'll need to do burst writes to SDRAM which might require a small data cache with 32byte lines, but check that the SDRAM interface doesn't merge sequential writes first.

At 100M ethernet a 100MHz nios has 32clocks per 32bit word to copy the data - probably just enough.