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I've seen serious problems due to unwanted interactions between TCP 'slow start', 'delayed acks' and Nagle (disabled) on zero-delay local networks with connections carrying uni-directional non-bulk traffic (ie relaying messages received on another network).
To ensure data is actually sent we had to send data in the reverse dircection at least every 4 ethernal packets.
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I've had similar problems, and found out that the cause was that the RX FIFO in the TSE component was much lower than the TCP window size reported by the Niche Stack (16k IIRC), and as the stack is too slow to receive a full burst some packets would be lost. Increasing the Rx FIFO size to something higher than the maximum TCP window size solved all our problems, but you must of course be sure that you have enough resources in the FPGA for that (especially if you plan to have simultaneous high speed TCP connections, and must increase the FIFO size even further).
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Please put some more light on your suggestion....i mean how do i do UDP reception in hardware as ..i am working at application layer, and UDP packet reception done on TCP/IP Stack & MAC/PHY layer.
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I think he is talking about this design (
http://www.alterawiki.com/wiki/nios_ii_udp_offload_example) which would indeed be the best choice for high performance UDP reception. I think there were some problems adapting this example to Quartus 11 though, but a search on the forum should give you more information.
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