Forum Discussion
Altera_Forum
Honored Contributor
16 years agoTry to localize the problem. For example:
1.Connect SignalTap to PCI IO on fully working FPGA, and compare bus configuration cycle with PCI standard. 2.Disconnect PCI from IO pad, connect to FPGA via JTAG and find out, does PCI IP core is working. 3.Check out the state of master-mode only PCI signals (REQ,GNT and so on). Or ask this question to mySupport at Altera.