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Altera_Forum's avatar
Altera_Forum
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18 years ago

NIOS2 DDR2 refrence desing

Dear friends,

does any body have solution for NIOS2 DDR2 in sopc builder, i tried with ddr2 documents but during complilation timing error, i dont know why, pleaese help me.

if any body have refrence design, please upload here, i am using custom statrix II board.

regards,

baba

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Hello,

    I think you are profession in my issues, I need your help.

    I have some troubles with my design with Stratix II devices. I use MegaWizard, Quartus's Web edition, to create ALTMEMPHY. It releases many files such as:

    *_alt_mem_phy_reconfig_sii

    *_alt_mem_phy_ sii

    alt_mem_phy_defines

    alt_mem_phy_sequencer.vhd

    *_altmem_phy_sequencer_wrapper.vo

    ...

    Module "alt_mem_phy_sequencer.vhd" is encrypted, so I can't see anything. How can I use this module?

    To ensure my logic is ok, I simulate them with my logic by using NCverilog 5.5. But the way ALTMEMPHY tool uses parameter is new to me. And when I run my simulation, it can not stop and print out may warnings. So you can give me your advice.

    I'm very impressed by ALTMEMPHY but I can't use it for a long time.

    Thank you in advance!
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    today is friday, 7.30 pm, so, detail solution tomorrow , no problem you can beat that

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    What timing issues are you running? What messages do you get within SOPC Builder or the Quartus II Compilation?

    More info buddy
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Hi babaship,

    What is the error message?

    I think that You must delete the following files list and regenerate your NIOS system.

    - add_constraints_for_< >.tcl

    - auto_add_ddr_constraints.tcl

    - auto_verify_ddr_timing.tcl

    - ddr_lib_path.tcl

    - remove_add_constraints_for_< >tcl

    - verify_timing_for_< >.tcl
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    --- Quote Start ---

    Hello,

    I think you are profession in my issues, I need your help.

    I have some troubles with my design with Stratix II devices. I use MegaWizard, Quartus's Web edition, to create ALTMEMPHY. It releases many files such as:

    *_alt_mem_phy_reconfig_sii

    *_alt_mem_phy_ sii

    alt_mem_phy_defines

    alt_mem_phy_sequencer.vhd

    *_altmem_phy_sequencer_wrapper.vo

    ...

    Module "alt_mem_phy_sequencer.vhd" is encrypted, so I can't see anything. How can I use this module?

    To ensure my logic is ok, I simulate them with my logic by using NCverilog 5.5. But the way ALTMEMPHY tool uses parameter is new to me. And when I run my simulation, it can not stop and print out may warnings. So you can give me your advice.

    I'm very impressed by ALTMEMPHY but I can't use it for a long time.

    Thank you in advance!

    --- Quote End ---

    Hi tuanna,

    You can simulate your NIOS system by using SOPC Builder. It can create a simulator project.