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Altera_Forum's avatar
Altera_Forum
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16 years ago

Nios II address range issue

Hi everybody,

I am using SOPC to built avalon interface for my custom external logic.i have selected NiosII as master and my custom logic as slave.Using new component Wizard, I have added signal and interface. In the interface i have selected avalon slave,i got an error before generation.

cpu_0:nois ii instruction master cannot address memories over 2^32.

cpu_0:nois ii data master cannot address memories over 2^32.

My data width is 32 but still getting error.

I have tried auto-assign base address and manually edit addresses also but no effect.what base address should i specify for my device.

Have anybody experienced this problem.

Pankaj

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You should not create a custom Avalon slave with a 32-bit address width. The maximum address space of the NIOS is 31 bits (upper bit is used for cache bypass). If you make a component with a 31-bit address space, there is no room for anything else on the processor's bus.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    It's not a data width issue, it's an address span issue. If the memory range that you're trying to address is >2^32, it won't work.

    Cheers,

    - Ura
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Jakobjones,

    Could you pls tell me what are the difference between Nios II instruction bus, address bus and data bus?

    In actual, does it mean that Nios II has only 2^31 of address bus/address spaces?

    Thx.

    Caridee
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Both the Instruction and Data master ports of the Nios II processor are used to address memory. Each master has a 32-bit address space but the highest bit is used by the Nios II processor to bypass the cache.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Jake,

    thank you for ur quick reply. Appreciate it!

    i wish to confirm last thing, is intruction and data master port are referring to instruction bus and data bus, repectively? If yes, means both instruction bus and data bus are having 2^31 address bus?

    thx for your confirmation, correct me if i am wrong.

    caridee
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yes, each master ( or bus if you wish) has a maximum address space of 31 bits.

    Jake