Nios CPU read FIFO

the data cache is between nios cpu and your avalon ip (fifo)

as long as the data cache "thinks" it holds the information last time read from the slave (fifo) it will deliver the value to the cpu instead of reading it again.

this ist because your ip modifies its data and therefor is some kind of master that modifies the data, what the cache won't recognise.

the data cache bypass with the highest adr bit set is a altera documented workaround. if bit 31 is set then nios will read from the ip directly (bypass the data cache)

so the fifo operations still has nothing to do with the adr. it can be the cache here

let me know if it works