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Altera_Forum's avatar
Altera_Forum
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15 years ago

Newbie Question: Access DPR outside SOPC Builder

Hi,

I'm currently having trouble to set up a connection to a megawizard created Dual Port RAM. I want to make it accessible from within NIOS as if it was a normal RAM inside NIOS-II via a DMA memory-to-memory access.

Is there an IP you can use for this type of access ? Do you need any kind of bridge for that? I can't believe that there is no IP for that kind of common issue.

I currently tried to build my "own" interface out of PIOs, but I can't do that because of latency issues, can I ?

See the attachments for further information.

I would highly appreciate your help!

Thx =)

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi andreg,

    I had the same need as you.

    Please refer to the following thread I started last month for some ideas:

    http://www.alteraforum.com/forum/showthread.php?t=24965

    Actually, I eventually ended up with a different and simpler approach.

    I instantiated the dpr external to the sopc system and used the sopc tristate bus to access it. In my design this was enough; maybe this is not good for your case if you have strong performance requirements.

    Regards

    Cris
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi andreg,

    I see wrong things in your code. Check if they are only copy and paste errors or actual code errors:

    - in alt_dma_rxchan_prepare(), the 4th parameter should be dma_done, namely the pointer to function to be called upon dma completion

    - you wait dma completion testing a rx_done variable, but you actually set the other variable dma_complete when dma completes

    - are you sure the tx_data and rx_buffer addresses you provide match those of memories connected to tx/rx dma: you should use system.h defines instead of numeric values.

    I have a design similar to your one and it works perfectly.

    I tried to use your same code (with the above corrections) and the dma performs correctly.

    The only differences being:

    - dma width is 16bits

    - tx dma is from external sram connected to sopc tristate bus

    - rx dma is to the main sdram and not a separate onchip memory

    (I don't think you need that descriptor memory; you are not using a sgdma module)

    Final note: pay attention to define rx_done as volatile, otherwise compiler may assume the while loop never ends.

    Regards

    Cris
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi andreg,

    Probably you have an error in tx_chan address and you are making dma transfer from the wrong memory area..

    Is the tristate bus width 32?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi,

    well I think I found some kind of reason for the problem.

    I changed some settings in the interface tab of the dpr interface (see attachment) and added a clock sink connected from sopc. It seems to work now, I'll figure it out.

    Eventually, the attachment can help someone.

    Thank you Cris72 for your fast and professional help! =)