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Naveena_P_Intel
New Contributor
New ContributorNeeds help on clarification on Scemi clock control
Stratix 10 1SG280LU3F50E1VG
Quartus 18.0.0.0 Build 2019 04/25/2018 SJ Pro Edition
Patches Installed: 0.06
We wanted advise on how to do Scemi clock control. I am using a PCIe HIP and using its clock as input to the DUT too in order to avoid any clock domain crossing issues with different clocks. So, I use this clock as uncontrolled clock and gate/ungate it to drive the controlled clock. There are 35 zceiClockControl instances and the controlled clock is ungated when each one of them is ready. This causes a lag in the controlled clock from uncontrolled.
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KennyT_alteraSuper Contributor
You can use clock control IP. You can refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-clkpll.pdf page 47. How do you measure the lag for the controlled clock from uncontrolled?- KennyT_alteraAny update?
Naveena_P_Intel No rigorous measurements - just from observing the signal tap logic analyzer output.
- KennyT_alteraYou have to check if you have written the correct constrain and the timing is closed for your design.
- KennyT_alteraany update?
