Needs help on clarification on Scemi clock control

Stratix 10 1SG280LU3F50E1VG

Quartus 18.0.0.0 Build 2019 04/25/2018 SJ Pro Edition

Patches Installed: 0.06

We wanted advise on how to do Scemi clock control. I am using a PCIe HIP and using its clock as input to the DUT too in order to avoid any clock domain crossing issues with different clocks. So, I use this clock as uncontrolled clock and gate/ungate it to drive the controlled clock. There are 35 zceiClockControl instances and the controlled clock is ungated when each one of them is ready. This causes a lag in the controlled clock from uncontrolled.