Naveena_P_IntelNew Contributor6 years agoNeeds help on clarification on Scemi clock control Stratix 10 1SG280LU3F50E1VG Quartus 18.0.0.0 Build 2019 04/25/2018 SJ Pro Edition Patches Installed: 0.06 We wanted advise on how to do Scemi clock control. I am using a PCIe HIP and using its c...Show More
KennyT_alteraSuper Contributor6 years agoYou have to check if you have written the correct constrain and the timing is closed for your design.
Recent DiscussionsWhy does Fitter show "Dedicated Pin" as "Reference Clock Source by" for downstream PLL in cascade?SolvedTeransceiver & FPGAAgilex‑7 F‑Tile Dynamic Reconfiguration Conflict Between HDMI and SDI RXJESD204B Multi-Link Implementation with AD9695 ADCs Having Different Lane Counts (L=4 and L=2)Cascaded Avalon Stream Multiplexer in Platform Design does not forward valid data packets