Need help simulating an NCO core (Label is unrelated)
Background:
I am doing support for an existing project that uses the NCO IP
I am trying to simulate that NCO IP
Running Quartus Prime Standard 18.1
Modelsim 2019.4
FPGA: 5CEBA4F17C7
The original authors of this system created the NCO called "nco_af"
The NCO IP is in a separate folder called nco_af
In this folder is a simulation/mentor folder
The platform designer created this dir under the NCO folder
It has this tcl script: msim_setup.tcl
This script has 2 parts, the top part (commented out) has what would be a
modelsim .do script, the second part is the compilation of the NCO IP parts
I did what the tcl script suggested and created a mentor.do script from the top part of the tcl script
I started modelsim
cd into the mentor dir and do mentor.do from modelsim
everything compiled,
the elab started,
a wave window came up then MS crashed
starting over
a modelsim.ini was created!!!
the libs for the sim are in the mentor dir
the same thing happened
the transcript window disappears and MS crashes
I was able to get the transcript saved to a file
there is a bunch of these:
Too few port connections for '<protected>'. Expected <protected>, found <protected>.
Protected: /nco_af/nco_ii_0/ux000/<protected> File: nco_af/simulation/submodules/mentor/asj_altqmcpipe.v Line: 38
it looks like the internals of the NCI IP are having a version issues
apparently there is a problem with these being simulated
These asj_ files are encrypted verilog...
THEN
I found this great support forum entry:
https://community.intel.com/t5/FPGA-Intellectual-Property/NCO-Simulation-help/m-p/224126
The suggestion was that I had to generate a simulation model for the NCO core
I followed the suggestions the author posted in the Nco_Steps.doc attachment
I get the same issue: modelsim is trying to use encrypted .v files
there were no "simulation models" vhdl files (I picked VHDL for simulation)
The msim_setup.tcl that quartus generated is using the encrypted .v files ?!?!?
THEN
I created a test NCO using the IP generator (not qsys)
I selected generate simulation in VHDL
It generated all the same support files as the existing qsys-generated NCO
the simulation fails the same way
Question:
How do I generate the VHDL simulation models for this IP?
Thanks
Ed