Occasional ContributorNCSIM of PLLs not generating correct output frequency
QuartusPrime 21.1 on CentOS7. Arria5 GX.
I have a PLL which accepts 104MHz (from an upstream) and is suppose to generate 182MHz and 91MHz. That is a multiply by 7 with a divide by 8 and divide by 4 to get the two output frequencies.
The PLL's were created inside Platform Designer.
I have other examples in this design of PLLs taking in reference clocks from other PLLs and being able to generate cascaded clocks.
I am rebuilding this design with a test point out to look at the 182MHz clock but am I missing something during my simulation. I am not seeing any errors in Platform Designer, but I will admit that many of the PLLs I have dropped into Platform Designer do not generate the Generic PLL report upon simulation startup.
If there is some switches I could set in NCSIM to enable verbose output from the PLLs in the Console Log those might be most helpful.
Thanks,
TomT...
Aqid, no simulation error just the waveform frequency is incorrect. I modified the PLL to accept 104MHz but on the input I changed to multiple by 7 and divide by 2 and then changed my output stages to account for the VCO frequency difference to get the right frequencies I needed. This does simulate properly and generates the correct clocks. I cannot explain it but this was my solution and I am moving forward.
